In designing a field programmable gate array (FPGA) or the like, a technique for verifying whether or not a timing error such as a critical path occurs is known.
In recent years, an FPGA installed with a plurality of functional blocks that operate at different frequencies and different voltages is being commercialized accompanying advancement of miniaturization and high functionality of the FPGA. Various FPGAs having different delay characteristics are provided according to a maker supplying the FPGA and a grade of a supplied FPGA.
A logic described with a register transfer level (RTL) by a circuit designer who designs a circuit to be installed on the FPGA is subjected to logic verification. The logic subjected to logic verification is subjected to logical synthesis so as to satisfy predetermined timing constraint to generate net information, and generated net information is subjected to arrangement and wiring, and arrangement and wiring data indicating arrangement and wiring information of a cell is generated. The generated arrangement and wiring data is subjected to timing verification and timing verification information indicating a signal path where a timing error such as a setup error and a hold error has occurred is output. In order to resolve the timing error of the signal path in which the timing error indicated by timing verification information has occurred, for each signal path in which the timing error has occurred, the circuit designer corrects the RTL in a case where it is impossible to resolve the timing error by changing arrangement and wiring data.
The circuit designer inserts flip-flops into the signal path where the timing error has occurred based on past experience and corrects the RTL so that the timing error is resolved. Since RTL correction is executed based on the past experience of the circuit designer, there is a concern that the timing error may not be resolved by correcting the RTL when the designer has little experience or the like. When the timing error is not resolved by RTL correction, there is a concern that a process from RTL correction to timing verification is repeated and design costs increase.
There is a concern that, in order to reliably resolve the timing error, the circuit designer may insert the flip-flops excessively in the signal path where the timing error has occurred. When the flip-flops are excessively inserted into the signal path where the timing error has occurred, the number of flip-flops having a relatively high operating frequency increases and the circuit scale of the FPGA increases more than demanded, and thus, power consumption of the FPGA increases.
The following is a reference document.
[Document 1] Japanese Laid-open Patent Publication No. 2008-123056.